1. Field of the Invention
The present invention relates to a clock control method and an integrated circuit element (hereinafter referred to as an IC), and particularly relates to an IC using a clock in the internal circuit thereof and a method of controlling the clock inside the IC.
2. Description of the Prior Art
The integration of circuits carries advantages of reduced packaging area through an increased degree of the integration and reduced cost manufacturing through a decreased number of components. As one example, a microcomputer having a clock generating circuit built therein is given on page 89 of "Hitachi Single-Chip RISC Microcomputer SH7032, SH7034, HD6417032, HD6477034, HD6437034 Hardware Manual (third edition)". FIG. 2 is a circuit diagram regarding a clock of this microcomputer.
As shown in FIG. 2, the circuit has two input terminals XTAL 2 and EXTAL 4, via which a signal is input and then transmitted to an oscillator 6. The input terminals XTAL and EXTAL are also connected to a crystal oscillator and a capacitive circuit in a known manner. A clock is oscillated by the oscillator 6, shaped in a duty correction circuit 8, and then supplied to the internal circuit of the microcomputer and an output terminal CK 10. The output terminal CK in turn supplies the clock to an external system of the microcomputer.
According to the microcomputer, the provision of the built-in oscillator 6 can decrease the number of components constituting the circuit, and the same clock can be used in the internal circuit and the external system. Therefore, timings can easily be controlled, both inside and outside the microcomputer.
As another advantage of the circuit integration, there is a high-speed operation of the circuit. In general, the delay of a gate in the IC is smaller than that of the equivalent external logic circuit constituted by discrete components. By incorporating the main part of the circuit into a single IC, the operation speed of the entire device is improved.
In order to improve operation speed, the employment of a high speed (high frequency) clock is necessary. When the high-speed clock is used, however, a problem of clock skew occurs. Clock skew refers to a deviation in timings of clocks, which should be originally the same, caused by gating or dividing the clocks. When a low-speed clock is used, in order to eliminate the clock skew, a delay gate can be incorporated in a relatively advanced clock, or other countermeasure can be taken. However, for example, in the 50 MHz clock having one cycle of only 20 ns, adjustment by means of the delay gate is limited. On the spot of design, there is a daily situation that even if one place is corrected, a timing violation arises in another place. When high-speed circuit operation is desired, avoiding malfunction caused by clock skew is important, but it is a remarkably intricate and laborious work.
In the aforementioned microcomputer, the clock appearing at the external terminal CK is delayed as much as an output buffer, as compared with the clock used in the internal circuit. When this microcomputer is manufactured so as to operate at, for example, 50 MHz, the delay of the output buffer is usually about several ns, which would produce a critical clock skew inside and outside the microcomputer as the case may be. Additionally, since the advanced clock is used in the microcomputer, the adjustment of timings by means of the external delay gate is usually unfeasible.